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copyright ? cirrus logic, inc. 2006 (all rights reserved) http://www.cirrus.com preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 192 khz stereo dac with 2 vrms line out features ? multi-bit delta-sigma modulator ? 24-bit resolution ? supports sample rates up to 192 khz ? 102 db a-wt dynamic range ? -90 db thd+n ? integrated line driver ? 2 vrms output into 5 k ac load ? analog low-pass filter ? stereo mutes with auto-mute function ? low clock-jitter sensitivity ? low-latency digital filtering ? popguard ? technology for control of clicks and pops ? single-ended outputs ? +3.3 core, +9 to 12 analog, and +1.5 to 3.3 interface power supplies ? low power consumption ? 20-pin tssop, lead-free assembly description the CS4352 is a complete stereo digital-to-analog sys- tem including digital interpolation, fifth-order multi-bit delta-sigma digital-to-analog conversion, digital de-em- phasis, analog filtering, and on-chip 2 vrms line-level driver. the advantages of this architecture include ideal differential linearity, no distortion mechanisms due to re- sistor matching errors, no linearity drift over time and temperature, high tolerance to clock jitter, and a minimal set of external components. the CS4352 is available in a 20-pin tssop package in commercial (-10c to +70c) grade. the cdb4352 customer demonstration board is also available for de- vice evaluation and implementation suggestions. please see ?ordering information? on page 19 for com- plete details. these features are ideal fo r cost-sensitive, 2-channel audio systems including video game consoles, dvd players, a/v receivers, se t-top boxes, digital tvs and dvd recorders, mini-component systems, and mixing consoles. pcm serial interface interpolation filter serial audio input left and right mute controls 2 vrms line level right channel output 2 vrms line level left channel output reset 1.5 v to 3.3 v hardware configuration level translator hardware control multibit ? modulator 3.3 v 9 v to 12 v interpolation filter amp + filter amp + filter multibit ? modulator auto speed mode detect dac dac external mute control internal voltage reference september '06 ds684pp1 CS4352
2 ds684pp1 CS4352 table of contents 1. pin description ........................................................................................................... ..................... 3 2. characteristics and specificat ions .......... ................. ................ ................ ................ ........... 4 specified operating conditions .............................................................................................. 4 absolute maximum ratings ...................................................................................................... .. 4 dac analog characteristics .................................................................................................... 5 combined interpolation & on-chip analog filter response .......... ................ .............. 6 switching specifications - serial audio interface .............. ............. ............. ........... 7 digital characteristics ....................................................................................................... ....... 8 power and thermal characteristics ................................................................................... 8 3. typical connection diagram ................................................................................................. .... 9 4. applications ............................................................................................................... .................... 10 4.6.1 capacitor placement ...... ............................................................................................... ........ 12 4.7.1 power-up ................................................................................................................ .............. 13 4.7.2 power-down .............................................................................................................. ............ 13 4.7.3 discharge time .......................................................................................................... ........... 13 5. digital filter response plots ......... ................ ................ ................ ................ .............. .. 15 6. parameter definitions ...................................................................................................... .......... 17 7. package dimensions ........................................................................................................ ........... 18 8. ordering information ...................................................................................................... ......... 19 9. revision history ........................................................................................................... ................. 19 list of figures figure 1.serial input timing .................................................................................................. ...................... 7 figure 2.typical connection diagram ........................................................................................... .............. 9 figure 3.i2s, up to 24-bit data ............................................................................................... ................... 11 figure 4.right-justified data ................................................................................................. .................... 11 figure 5.left-justified up to 24-bit data ....... .............................................................................. ............... 11 figure 6.de-emphasis curve .................................................................................................... ................ 12 figure 7.single-speed stopband rejection ...................................................................................... ........ 15 figure 8.single-speed transition band ......................................................................................... ........... 15 figure 9.single-speed transition band (detail) ................................................................................ ........ 15 figure 10.single-speed passband ripple ........................................................................................ ........ 15 figure 11.double-speed stopband rejection ..................................................................................... ...... 15 figure 12.double-speed transition band .............. .......................................................................... ......... 15 figure 13.double-speed transition ba nd (detail) ............................................................................... ...... 16 figure 14.double-speed passband ripple ........................................................................................ ....... 16 figure 15.quad-speed stopband rejection ....................................................................................... ...... 16 figure 16.quad-speed transition band .......................................................................................... ......... 16 figure 17.quad-speed transition band (detail) ................................................................................. ...... 16 figure 18.quad-speed passband ripple .......................................................................................... ....... 16 list of tables table 1. CS4352 auto-detect ................................................................................................... ................ 10 table 2. single-speed mode standard frequencies ............................................................................... .10 table 3. double-speed mode standard frequencies ............................................................................... 10 table 4. quad-speed mode standard frequencies . ................................................................................ 10 table 5. digital interface format ............................................................................................. .................. 11
ds684pp1 3 CS4352 1. pin description pin name pin # pin description sdin 1 serial audio data input ( input ) - input for two?s complement serial audio data. sclk 2 serial clock ( input ) - serial clock for the serial audio interface. lrck 3 left / right clock ( input ) - determines which channel, left or right, is currently active on the serial audio data line. mclk 4 master clock ( input ) - clock source for the delta-sigma modulator and digital filters. vd 5 digital power ( input ) - positive power supply for the digital section. gnd 6 16 ground ( input ) - ground reference. dif0 dif1 8 7 digital interface format ( input ) - defines the required relationship between the left/right clock, serial clock, and serial audio data. dem 9 de-emphasis ( input ) - selects the standard 15 s/50 s digital de-emphasis filter response for 44.1 khz sample rates rst 10 reset ( input ) - powers down the device and resets all internal registers to their default settings when enabled. va 11 low voltage analog power ( input ) - positive power supply for the analog section. vbias 12 positive voltage reference ( output ) - positive reference voltage for the internal dac. vq 13 quiescent voltage ( output ) - filter connection for internal quiescent voltage. va_h 17 high voltage analog power ( input ) - positive power supply for the analog section. vl 20 serial audio interface power ( input ) - positive power for the serial audio interface bmutec amutec 14 19 mute control ( output ) - control signal for optional mute circuit. aoutb aouta 15 18 analog outputs ( output ) - the full-scale analog line output level is specified in the analog characteris- tics table. sdin vl sclk amutec lrck aouta mclk va_h vd gnd gnd aoutb dif1 bmutec dif0 vq dem vbias rst va 1 2 3 4 5 6 7 8 9 10 11 12 17 18 19 20 13 14 15 16
4 ds684pp1 CS4352 2. characteristics a nd specifications (min/max performance characteristics and specifications are guaranteed over the specified operating conditions. typical specifications are derived from performance measurements at t a = 25 c, va_h = 9 v, va = 3.3 v, vd = 3.3 v.) specified operating conditions (gnd = 0 v; all voltages with respect to ground.) absolute maximum ratings (gnd = 0 v; all voltages with respect to ground.) operation at or beyond these limits may result in permane nt damage to the device. normal operation is not guar- anteed at these extremes. parameters symbol min typ max units dc power supply high voltage analog power low voltage analog power digital power interface power v a_h v a v d v l 8.40 3.13 3.13 1.43 9 3.3 3.3 1.5 12.6 3.47 3.47 3.47 v v v v specified temperature range t a -10 - +70 c parameters symbol min max units dc power supply high voltage analog power low voltage analog power digital power interface power v a_h v a v d v l -0.3 -0.3 -0.3 -0.3 14 3.63 3.63 3.63 v v v v input current, any pin except supplies i in -10ma digital input voltage digital interface v in-l -0.3 v l + 0.4 v ambient operating temperature (power applied) t a -55 +125 c storage temperature t stg -65 +150 c
ds684pp1 5 CS4352 dac analog characteristics (test conditions (unless otherwise spec ified): input test signal is a 997 hz sine wave at 0 dbfs; measurement bandwidth 10 hz to 20 khz) 1. one-half lsb of triangular pdf dither is added to data. parameter symbol min typ max unit all speed modes fs = 48, 96, and 192 khz dynamic range (note 1) 24-bit a-weighted unweighted 16-bit a-weighted unweighted 96 93 - - 102 99 98 95 - - - - db db db db total harmonic distortion + noise (note 1) 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db thd+n - - - - - - - -90 -79 -39 -90 -75 -35 -84 -73 -33 - - - db db db db db db idle channel noise / signal-to-noise ratio (a-wt) - 102 - db interchannel isolation (1 khz) - 90 - db analog output - all modes full scale output voltage 1.9 2.0 2.1 vrms common mode voltage v q -4-vdc max current draw from an aout pin i outmax - 575 - a max current draw from vq i qmax -1- a interchannel gain mismatch - 0.1 - db gain drift - 100 - ppm/c output impedance z out -50- ac-load resistance r l 5--k load capacitance c l --100pf
6 ds684pp1 CS4352 combined interpolat ion & on-chip analog filter response (the filter characteristics have been normalized to the sa mple rate (fs) and can be re ferenced to th e desired sam- ple rate by multiplying the given characteristic by fs.) 2. response is clock-dependent and will scale with fs. 3. for single-speed mode, the measurement bandwidth is from stopband to 3 fs. for double-speed mode, the measurement bandwidth is from stopband to 3 fs. for quad-speed mode, the measurement bandwidth is from stopband to 1.34 fs. 4. de-emphasis is available only in single-speed mode. 5. amplitude vs. frequency plots of this data are available in ?digital filter response plots? on page 15 . parameter min typ max unit combined digital and on-chip analog filter response - single-speed mode - 48 khz passband (note 2) to -0.01 db corner to -3 db corner 0 0 - - .454 .499 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 db stopband 0.547 - - fs stopband attenuation (note 3) 102 - - db total group delay (fs = output sample rate) - 9.4/fs - s intra-channel phase deviation - - 0.56/fs s inter-channel phase deviation - - 0 s de-emphasis error (note 4) (relative to 1 khz) fs = 44.1 khz - - 0.14 db combined digital and on-chip analog filter response - double-speed mode - 96 khz passband (note 2) to -0.01 db corner to -3 db corner 0 0 - - .430 .499 fs fs frequency response 10 hz to 20 khz -0.01 - 0.01 db stopband .583 - - fs stopband attenuation (note 3) 80 - - db total group delay (fs = output sample rate) - 4.6/fs - s intra-channel phase deviation - - 0.03/fs s inter-channel phase deviation - - 0 s combined digital and on-chip analog filter response - quad-speed mode - 192 khz passband (note 2) to -0.01 db corner to -3 db corner 0 0 - - .105 .490 fs fs frequency response 10 hz to 20 khz -0.01 - 0.01 db stopband .635 - - fs stopband attenuation (note 3) 90 - - db total group delay (fs = output sample rate) - 4.7/fs - s intra-channel phase deviation - - 0.01/fs s inter-channel phase deviation - - 0 s
ds684pp1 7 CS4352 switching specifications - seri al audio interface parameters symbol min max units mclk frequency 1.024 51.2 mhz mclk duty cycle 45 55 % input sample rate (auto selection) single-speed mode double-speed mode quad-speed mode fs fs fs 4 84 170 54 108 216 khz khz khz lrck duty cycle 40 60 % sclk pulse width low t sclkl 20 - ns sclk pulse width high t sclkh 20 - ns sclk period single-speed mode t sclkw -- double-speed mode t sclkw -- quad-speed mode t sclkw -- sclk rising to lrck edge delay t slrd 20 - ns sclk rising to lrck edge setup time t slrs 20 - ns sdin valid to sclk rising setup time t sdlrs 20 - ns sclk rising to sdin hold time t sdh 20 - ns sclkh t slrs t slrd t sdlrs t sdh t sclkl t sdata sclk lrck figure 1. serial input timing 1 128 () fs --------------------- - 1 64 () fs ------------------ 2 mclk -----------------
8 ds684pp1 CS4352 digital characteristics power and therma l characteristics 6. current consumption increases with increasing fs and increasing mclk. typ and max values are based on highest fs and highest mclk. va riance between speed modes is small. 7. power down mode is defined as rst pin = low with all clock and data lines held static low. all digital inputs have a weak pull-down which is only presen t during reset. opposing this pull-down will slightly increase the power-down current (pull-down is equivalent to a 50 k resistor per pin). 8. valid with the recommended capacitor values on vq and v bias as shown in the typical connection dia- gram in section 3 . parameters symbol min typ max units high-level input voltage vl = 3.3 v vl = 2.5 v vl = 1.5 v v ih v ih v ih 2.0 1.7 1.05 - - - - - - v v v low-level input voltage vl = 3.3 v vl = 2.5 v vl = 1.5 v v il v il v il - - - - - - 0.8 0.7 0.40 v v v input leakage current i in --10 a input capacitance - 8 - pf maximum mutec drive current - 2 - ma mutec high-level output voltage v oh -va_h- v mutec low-level output voltage v ol -0- v parameters symbol min typ max units power supplies power supply current normal operation, v a_h = 12 v (note 6) v a_h = 9 v v a = 3.3 v v d = 3.3 v interface current v l = 3.3 v power-down state, all supplies (note 7) i a_h i a_h i a i d i l i pd - - - - - - 10 9 3 8 0.1 200 13 12 4 11 0.5 - ma ma ma ma ma a power dissipation (all supplies) (note 6) va_h = 12 v normal operation power-down (note 7) va_h = 9 v normal operation power-down (note 7) - - - - 158 1 119 1 212 - 164 - mw mw mw mw power supply rejection ratio (note 8) (1 khz) (60 hz) psrr - - 60 60 - - db db
ds684pp1 9 CS4352 3. typical conn ection diagram digital audio source vl g n d mclk vd aouta 0.1 f 10 f +3.3 v * mode configuration sdin dif1 dif0 dem optional mute circuit rst bmutec 3.3 f left out vbias+ vq lrck sclk 3.3 f 10 k 560 aoutb 3.3 f va_h 0.1 f 10 f g nd 0.1 f +1.5 v to vd +9 v to +12 v amutec va 0.1 f 10 f +3.3 v 5.1 ? 2.2 nf* *optional *shown value is for fc=130 khz *remove this supply if optional resistor is present. the decoupling caps should remain. 1 2 3 4 20 10 7 8 9 6 15 5 11 12 17 19 18 optional mute circuit right out 3.3 f 10 k 560 2.2 nf* 14 15 13 figure 2. typical connection diagram CS4352
10 ds684pp1 CS4352 4. applications 4.1 sample rate range/operational mode detect the device operates in one of three operational modes. the allowed sample rate range in each mode is auto-detected. the CS4352 will auto-de tect the correct mode when the input sample ra te (fs), defined by the lrck fre- quency, falls within one of the ranges illustrated in table 1 . sample rates outside the specified range for each mode are not supported. table 1. CS4352 auto-detect 4.2 system clocking the device requires external generation of the master (mclk), left/right (lrck) and serial (sclk) clocks. the left/right clock, defined al so as the input sample rate (f s ), must be synchronously derived from the mclk according to specified ratios. the specified rati os of mclk to lrck, along with several standard au- dio sample rates and the required mclk frequency, are illustrated in tables 2 - 4 . refer to section 4.3 for the required sclk timing associated with the selected digital interface format and to ?switching specifications - serial audio interface? on page 7 for the maximum allowed clock frequencies. table 2. single-speed mode standard frequencies table 3. double-speed mode standard frequencies table 4. quad-speed mode standard frequencies input sample rate (f s )mode 4 khz - 54 khz single-speed mode 84 khz - 108 khz double-speed mode 170 khz - 216 khz quad-speed mode sample rate (khz) mclk (mhz) 256x 384x 512x 768x 1024x 32 8.1920 12.2880 16.3840 24.5760 32.7680 44.1 11.2896 16.9344 22.5792 33.8688 45.1584 48 12.2880 18.4320 24.5760 36.8640 49.1520 sample rate (khz) mclk (mhz) 128x 192x 256x 384x 512x 88.2 11.2896 16.9344 22.5792 33.8688 45.1584 96 12.2880 18.4320 24.5760 36.8640 49.1520 sample rate (khz) mclk (mhz) 128x 192x 256x 176.4 22.5792 33.8688 45.1584 192 24.5760 36.8640 49.1520
ds684pp1 11 CS4352 4.3 digital interface format the device will accept audio samples in 1 of 4 digital in terface formats, as illustrated in table 5 . the desired format is selected via th e dif1 and dif0 pins. for an illustra tion of the required relationship between the lrck, sclk and sdin, see figures 3 - 5 . for all formats, sdin is valid on the rising edge of sclk. also, sclk must have at least 32 cycles per lrck period in format 2 and 48 cycles per lrck period in format 3. for more information about serial audio formats, refer to cirrus logic application note an282. the 2-channel serial audio interface: a tutorial , available at www.cirrus.com . table 5. digital interface format figure 3. i2s, up to 24-bit data figure 4. right-justified data figure 5. left-justifi ed up to 24-bit data dif1 dif0 description format figure 00 i2s, up to 24-bit data 0 3 01 right-justified, 24-bit data 1 4 10 left-justified, up to 24-bit data 2 5 11 right-justified, 16-bit data 3 4 lrck sclk left channel right channel sdin +3 +2 +1 +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 msb lsb lsb lrck sclk left channel sdin -6 -5 -4 -3 -2 -1 -7 +1 +2 +3 +4 +5 msb right channel lsb msb +1 +2 +3 +4 +5 lsb -6 -5 -4 -3 -2 -1 -7 msb lrck sclk left channel right channel sdin +3 +2 +1 +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 lsb msb lsb
12 ds684pp1 CS4352 4.4 de-emphasis control the device includes on-chip digital de-emphasis. figure 6 shows the de-emphasis curve for fs equal to 44.1 khz. the frequency response of the de-emphasis curve scales with changes in sample rate, fs. the de-emphasis error will increase for sample rates other than 44.1 khz when pulled to vl, the dem pin activates the 44.1 kh z de-emphasis filter. when pulled to gnd, the dem pin turns off the de-emphasis filter. note: de-emphasis is only availa ble in single-speed mode. 4.5 recommended power-up sequence 1. hold rst low until the power supplies an d configuration pins are stable, and the master and left/right clocks are locked to the appropriate frequencies, as discussed in section 4.2 . in this state, vq will re- main low and vbias will be connected to va. 2. bring rst high. the device will remain in a low power state with vq low and will initiate the power-up sequence after approximately 512 lrck cycles in single-speed mode (1024 lrck cycles in double- speed mode, and 2048 lrck cycles in quad-speed mode). 4.6 grounding and power supply arrangements as with any high-resolution converter, the CS4352 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. figure 2 shows the recommended power ar- rangements, with va_h, va, vd, and vl connected to clean supplies. if the ground planes are split between digital ground and analog ground, the gnd pins of th e CS4352 should be connected to the analog ground plane. all signals, especially clocks, should be kept away from the vbias and vq pins in order to avoid unwanted coupling into the dac. 4.6.1 capacitor placement decoupling capacitors should be placed as close to the dac as possible, with the low-value ceramic ca- pacitor being the closest. to further minimize impeda nce, these capacitors should be located on the same layer as the dac. if desired, all supply pins may be connected to the same supply, but a decoupling ca- pacitor should still be placed on each supply pin. note: all decoupling capacitors should be referenced to analog ground. the cdb4352 evaluation board demonstrates the optimum layout and power supply arrangements. gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz figure 6. de-emphasis curve
ds684pp1 13 CS4352 4.7 popguard transient control the CS4352 uses a novel technique to minimize the effects of output transients during power-up and power- down. this technology, when used wit h external dc-blocking capacitors in series with the audio outputs, minimizes the audio transients commonl y produced by single-ended, single -supply converters. it is activat- ed inside the dac when the rst pin is toggled and requires no other external control, aside from choosing the appropriate dc-blocking capacitors. 4.7.1 power-up when the device is initially powe red-up, the audio outputs, aouta and aoutb, are clamped to gnd. following a delay of approximately 1000 sample peri ods, each output begins to ramp toward the quies- cent voltage. approximately 10,000 lrck cycles later, the outputs reach v q and audio output begins. this gradual voltage ramping allows time for the exte rnal dc-blocking capacitors to charge to the quies- cent voltage, minimizing au dible power-up transients. 4.7.2 power-down to prevent audible transients at power-down, the devi ce must first enter its power-down state. when this occurs, audio output ceases, and th e internal output buffers are disconnected from aouta and aoutb. in their place, a soft-start current sink is substituted that allows the dc-blocking capacitors to slowly dis- charge. once this charge is dissipated, the power to th e device may be turned off, and the system is ready for the next power-on. 4.7.3 discharge time to prevent an audio transient at the next power-on , the dc-blocking capacitors must fully discharge be- fore turning on the power or exitin g the power-down state. if full disc harge does not occur, a transient will occur when the audio outputs are initially clamped to gnd. the time that the device must remain in the power-down state is related to the value of the dc-bl ocking capacitance and the output load. for example, with a 3.3 f capacitor, the minimum power-do wn time will be approximately 0.4 seconds. 4.8 mute control the mute control pins go active during power-up initializ ation, reset, muting, or if the mclk to lrck ratio is incorrect. these pins are intended to be used as c ontrol for external mute circ uits to prevent the clicks and pops that can occur in any single-ended, single-supply system. use of the mute control function is not mandatory but recommended for designs requiring the absolute min- imum in extraneous clicks and pops. also, use of th e mute control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit. please see the cdb4352 data sheet for a suggested mute circuit for dual-supply s ystems. alternately, the fet muting circuit from the cs4351 data sheet may be used as well. this fet circuit must be placed in series after the rc filter ; otherwise noise may occur during muting conditions. further esd protection will need to be taken into consideration for the fet used.
14 ds684pp1 CS4352 4.9 initialization and powe r-down sequence diagram user: apply power wait state user: apply mclk, sclk, and lrck mclk/lrck ratio detection user: remove lrck or mclk user: change mclk/lrck ratio analog output is generated user: apply rst user: apply mclk, sclk, lrck, and release rst power-down state vq and outputs low vq and outputs ramp down vq and outputs ramp up
ds684pp1 15 CS4352 5. digital filter respon se plots 0.4 0.5 0.6 0.7 0.8 0.9 1 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0. 6 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency(normalized to fs) amplitude (db) figure 7. single-speed stopband rejectio n figure 8. single-speed transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0. 5 ?0.02 ?0.015 ?0.01 ?0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 9. single-speed transition band (detail) figure 10. single-speed passband ripple 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0. 6 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 11. double-speed stopband rejection figure 12. double-speed transition band
16 ds684pp1 CS4352 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0. 5 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 13. double-speed transition band (det ail) figure 14. double-speed passband ripple 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 15. quad-speed stopband rejection figure 16. quad-speed transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.2 5 0.2 0.15 0.1 0.05 0 0.05 0.1 0.15 0.2 frequency(normalized to fs) amplitude (db) figure 17. quad-speed transition band (detail) figure 18. quad-speed passband ripple
ds684pp1 17 CS4352 6. parameter definitions total harmonic distortion + noise (thd+n) the ratio of the rms value of the signal to the rms su m of all other spectral components over the specified bandwidth (typically 10 hz to 20 khz), including distortion comp onents. expressed in decibels. dynamic range the ratio of the full-scale rms value of the signal to the rms sum of all other spec tral components over the specified bandwidth. dynamic range is a signal-to-noi se measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is then added to the re sulting measurement to refer the measurement to full scale. this technique ensures that t he distortion components are below the noise level and do not effect the measurement. this measurement technique has been accepted by the audio engineering society, aes17- 1991, and the electronic industries association of japan, eiaj cp-307. interchannel isolation a measure of crosstalk between the left and right chan nels. measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. units in deci- bels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full-scale an alog output for a full-scale digital input. gain drift the change in gain value with temperature. units in ppm/c. intra-channel phase deviation the deviation from linear phase within a given channel. inter-channel phase deviation the difference in phase between channels.
18 ds684pp1 CS4352 7. package dimensions 1. ?d? and ?e1? are reference datums and do not incl uded mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. dimension ?b? does not include dambar protrusi on/intrusion. allowable dambar protrusion shall be 0.13 mm total in excess of ?b? dimension at maximum material condition. dambar intrusion shall not re- duce dimension ?b? by more than 0. 07 mm at least material condition. 3. these dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. inches millimeters note dim min nom max min nom max a -- -- 0.043 -- -- 1.10 a1 0.002 0.004 0.006 0.05 -- 0.15 a2 0.03346 0.0354 0.037 0.85 0.90 0.95 b 0.00748 0.0096 0.012 0.19 0.245 0.30 2 , 3 d 0.252 0.256 0.259 6.40 6.50 6.60 1 e 0.248 0.2519 0.256 6.30 6.40 6.50 e1 0.169 0.1732 0.177 4.30 4.40 4.50 1 e -- -- 0.026 -- -- 0.65 l 0.020 0.024 0.028 0.50 0.60 0.70 0 4 8 0 4 8 jedec #: mo-153 controlling dimension is millimeters. parameters symbol min typ max units package thermal resistance 20l tssop ja -72-c/watt 20l tssop (4.4 mm body) package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view
ds684pp1 19 CS4352 8. ordering information 9. revision history release changes a1 initial release pp1 lowered va_h min specification updated idle channel noise specification to a-wt updated aout current draw specification updated vil for vl=1.5v product description package pb-free grade temp range container order # CS4352 20-pin, 192 khz stereo dac with 2 vrms line out 20-pin tssop yes commercial -10 to +70 c rail CS4352-czz commercial -10 to +70 c tape & reel CS4352-czzr cdb4352 CS4352 evaluation board - - - - cdb4352 contacting cirrus logic support for all product questions and inquiries, c ontact a cirrus logic sales representative. to find the one nearest you, go to www.cirrus.com. important notice "preliminary" product information describes products that are in production, but for which full characterization data is not ye t available. cirrus logic, inc. and its sub- sidiaries ("cirrus") believe that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to obtain the latest version of re levant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and condit ions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnif ication, and limitation of liability. no responsibility is assu med by cirrus for the use of this informa- tion, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or ot her rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, m ask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the information contained herei n and gives consent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of c irrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resal e. certain applications usin g semiconductor products may involve potential ri sks of death, personal injury, or severe prop- erty or environmental damage (?critical applications?). cirrus products are not designed, authorized or warranted for use in aircraft systems, military a pplications, products s urgically implanted into the body, automotive sa fety or security de- vices, life support products or other cri tical applications. i nclusion of cirrus products in su ch applications is understood to be fully at the customer?s risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantability and fitness for particular purp ose, with regard to any cirrus product that is used in such a manner. if the customer or cus tomer?s customer uses or permits the use of ci rrus products in critical applica- tions, customer agrees, by such use, to fully indemnify cirrus, its o fficers, directors, employee s, distributors and other agents from any and all liability, including attorneys? fees a nd costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, the cirrus logic logo designs, and popguard are trademarks of cirrus logic, inc. all other brand and prod uct names in this document may be trademarks or service marks of their respective owners.

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